Advanced Data Structures by Saha Suman; Shukla Shailendra;

Author:Saha, Suman; Shukla, Shailendra;
Language: eng
Format: epub
Publisher: CRC Press LLC
Published: 2019-06-06T00:00:00+00:00

8.2 Cache Oblivious Algorithms

8.2.1 Cache aware model

The memory system of most modern computers consists of a hierarchy of memory levels, with each level acting as a cache for the next; for a typical desktop computer the hierarchy consists of registers, level 1 cache, level 2 cache, level 3 cache, main memory, and disk. The model defines a computer as having two levels: 1. The cache which is near the CPU, cheap to access, but limited in space. 2. The disk which is distant from the CPU, expensive to access, but nearly limitless in space. The main aspect of this model is that transfers between cache and disk involve blocks of data. As a consequence of this, the memory access pattern of an algorithm has a major influence on its practical running time. If the program is aware of the cache hardware, the information can be used to optimize the cache complexity for the particular cache size and line length.

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